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Typical Application Information
1. Normal Operating Consideration
The FAN7383 is a single PWM input half-bridge gate-
3. Layout Consideration
For optimum performance of high- and low-side gate
drive IC with programmable dead-time and shutdown
drivers, cannot be achieved
without taking due
function.
The dead-time is set with a resistor (R DT ) at the DT pin.
The wide dead-time programming range provides the
flexibility to optimize drive signal timing for a selection of
switching devices (MOSFET or IGBT) and applications.
The turn-on time delay circuitry (Dead-Time)
accommodates resistor values from 0 Ω to 200k Ω with a
dead-time proportional to the R DT resistance.
Grounding the DT pin programs the FAN7383 to drive
both outputs with minimum dead time.
If the SD pin voltage decrease below 1.2V in normal
operation, the IC enters the shutdown mode.
2. Under-Voltage Lockout (UVLO)
The FAN7383 has an under-voltage lockout (UVLO)
protection circuitry for high and low side channels to
prevent malfunction when V DD or V BS is lower than the
specified threshold voltage. The UVLO circuitry monitors
the supply voltage (V DD ) and bootstrap capacitor voltage
(V BS ) independently.
? 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
14
considerations must be taken during printed circuit board
(PCB) layout.
3.1 Supply Capacitors
If the output stages are able to quickly turn on the
switching device with high value of current, the supply
capacitors must be placed as close as possible to the
device pins (V DD and GND for the ground-tied supply, V B
and V S for the floating supply) to minimize parasitic
inductance and resistance.
3.2 Gate Drive Loop
Current loops behave like an antenna, able to receive
and transmit noise. To reduce the noise coupling/
emission and improve the power switch turn-on and off
performances, gate drive loops must be reduced as
much as possible.
3.3 Ground Plane
Ground plane must not be placed under or nearby the
high-voltage floating side to minimize noise coupling.
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